Design of Low Power Vlsi Circuits Using Cascode Logic Style

Due to the trade-off between power, area and performance, various efforts have been done. This work is also based to reduce the power dissipation of the vlsi circuits with the performance upto the acceptable level. The dominant term in a well designed vlsi circuit is the switching power and low-power design thus becomes the task of minimizing this switching power. So, to design a low-power vlsi circuit, it is preferable to use Non-clocked logic styles as they have less switching power. In this work various Non-clocked logic styles are compared by performing transistor level simulations for half adder circuit using TSMC 0.18 μm Technology and Eldo simulator of Mentor graphics. Keywords— Low-power, Non-clocked logic style, Half adder, DCVS, DSL, CNTL.